Semiconductor memory device which includes memory cell having charge accumulation layer and control gate

ABSTRACT

A semiconductor memory device includes a memory cell array, a power source circuit, a sense amplifier, a control circuit, and a processor. The memory cell array includes a nonvolatile memory cell. The power source circuit includes a first register and generates a voltage. The sense amplifier includes a second register, reads from the memory cell and amplifies the read data. The control circuit includes a third register and controls operations of the power source circuit and the sense amplifier. The processor controls the operations of the power source circuit, the sense amplifier and the control circuit by giving an instruction to the first to third registers. The control circuit decodes the instruction received at the third register so as to control the power source circuit and the sense amplifier directly based on a result of decoding.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2007-014057, filed Jan. 24, 2007,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device. Moreparticularly, the invention relates to a semiconductor memory whichincludes a memory cell having a charge accumulating layer and a controlgate.

2. Description of the Related Art

Conventionally, an electrically erasable and programmable ROM (EEPROM)has been well known as a nonvolatile semiconductor memory which isrewritable electrically. A method for controlling the EEPROM using amicrocomputer has been disclosed in, for example, Jpn. Pat. Appln. KOKAIPublication No. 2002-269065.

In case of controlling the EEPROM by a microcomputer, a flash memorycircuit is controlled using a signal with small bits which is suppliedfrom a processor and which is transmitted by address line, data line andwrite control line. Therefore, this has an advantage that the quantityof the signal wires can be reduced. Further, change and correction ofthe content of automatic control by the microcomputer are carried out bychanging and correcting software for operating the processor. Thus,there is such a merit that correction of a circuit itself is notrequired, thereby suppressing cost of manufacturing process.

However, as demerits of EEPROM control by a microcomputer, a time-lag isgenerated from an input of automatic operation start command up tostartup of the microcomputer and the quantity of signal wires which canbe controlled at a time is limited, thereby retarding the processing.

BRIEF SUMMARY OF THE INVENTION

A semiconductor memory device according to an aspect of the presentinvention includes:

a memory cell array which includes a nonvolatile memory cell;

a power source circuit which includes a first register and generates avoltage to be used in at least any one of write, erase and read of datawith respect to the memory cell;

a sense amplifier which includes a second register, reads data from thememory cell and amplifies the read data;

a control circuit which includes a third register and controlsoperations of the power source circuit and the sense amplifier; and

a processor which controls the operations of the power source circuit,the sense amplifier and the control circuit by giving an instruction tothe first to third registers, the control circuit decoding theinstruction of the processor received at the third register so as tocontrol the power source circuit and the sense amplifier directly basedon a result of decoding.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a block diagram of a flash memory according to a firstembodiment of the present invention;

FIG. 2 is a circuit diagram of a memory cell array according to thefirst embodiment of the present invention;

FIG. 3 is a circuit diagram of a control circuit according to the firstembodiment of the present invention;

FIG. 4 is a block diagram of a flash memory according to a secondembodiment of the present invention;

FIG. 5 is a circuit diagram of a switch circuit and a control circuitaccording to the second embodiment of the present invention;

FIG. 6 is a flow chart showing an operation of the flash memoryaccording to the second embodiment of the present invention;

FIG. 7 is a timing chart of various kinds of signals when the flashmemory is operated according to the second embodiment of the presentinvention;

FIG. 8 is a circuit diagram of a switch circuit, control circuit andpower source circuit according to a third embodiment of the presentinvention;

FIG. 9 is a flow chart showing an operation of a flash memory accordingto the third embodiment of the present invention;

FIG. 10 is a timing chart of various kinds of signals when the flashmemory is operated according to the third embodiment of the presentinvention;

FIG. 11 is a block diagram of a memory cell array according to a fourthembodiment of the present invention;

FIG. 12 is a block diagram of the memory cell array according to thefourth embodiment of the present invention, showing the concept of averification operation;

FIG. 13 is a circuit diagram of a verification circuit according to thefourth embodiment of the present invention;

FIG. 14 is a flow chart showing an operation of a flash memory accordingto the fourth embodiment of the present invention;

FIG. 15 and FIG. 16 are circuit diagrams of the verification circuitaccording to the fourth embodiment of the present invention;

FIG. 17 is a block diagram of a memory cell array according to amodification of the fourth embodiment of the present invention; and

FIG. 18 is a circuit diagram of the verification circuit according to amodification of the fourth embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION First Embodiment

A semiconductor memory device according to a first embodiment of thepresent invention will be described. FIG. 1 is a block diagram of a NORtype flash memory according to this embodiment. The NOR type flashmemory of this embodiment has two operation modes, i.e., first operationmode and second operation mode. The first operation mode is an operationmode which automatically executes read, write and erase of datasynchronously with a clock under the control of the CPU and hereinafter,is sometimes called automatic operation mode. The second operation modeis an operation mode which is executed independently of the control ofthe CPU and hereinafter, is sometimes called non-automatic operationmode.

As shown in FIG. 1, a NOR type flash memory 1 includes a microcomputer2, an input buffer 3, an I/O buffer 4, an address buffer 5, a memorycell portion 6, a sense amplifier 7, a verification circuit 8, ananalyzing circuit 9, an oscillation circuit 10, a power source circuit11, a control circuit 12 and a holding circuit 13. Each of theabove-mentioned circuit blocks 5-8, 11-13 has a register for receivingan instruction from the microcomputer. Upon transmission of signalsbetween the microcomputer 2 and each of the circuit blocks 5-8, 11-13, aread bus and a write bus are used for read of data and write of data,respectively.

The microcomputer 2 includes a CPU 20 and a memory 21. The memory 21holds instructions to be executed by the CPU 20. The CPU 20 executes aninstruction held in the memory 21 under the automatic operation mode soas to control the operations of the circuit blocks 5-8, 11-13. When theCPU 20 outputs an instruction to the circuit blocks 5-8, 11-13 under theautomatic operation mode, the circuit blocks 5-8, 11-13 receive theinstructions through a register. The respective circuit blocks 5-8,11-13 decode the received instruction and executes the giveninstruction.

The input buffer 3 receives an address given from outside. Then, thereceived address is output to the address buffer 5 and the analyzingcircuit 9.

The I/O buffer 4 receives write data and command given from outside. Thereceived write data is output to the verification circuit 8 and thecommand is output to the analyzing circuit 9. Read data given from theverification circuit 8 is output to outside.

The address buffer 5 holds an address given from the I/O buffer 3 andoutputs the address to the memory cell portion 6 and the analyzingcircuit 9.

The memory cell portion 6 includes a nonvolatile memory cell, whichmemorizes data given from outside. The memory cell portion 6 includes amemory cell array in which memory cells are arranged in matrixconfiguration, a row decoder which selects the row direction of thememory cell array and a column decoder which selects the columndirection. An address given from the address buffer is input to the rowdecoder and column decoder. FIG. 2 is a circuit diagram of the memorycell array having the memory cell portion 6.

As shown in FIG. 2, the memory cell array includes ((m+1)×(n+1)) (m, nare natural numbers) memory cells MC. The memory cell MC is a MOStransistor having a stacked gate which includes a charge accumulationlayer (for example, a floating gate in the present embodiment) and acontrol gate.

The configuration of the stacked gate is as follows. That is, the chargeaccumulation layer is formed on the semiconductor substrate with a gateinsulating film interposed therebetween and the control gate is formedon the charge accumulation layer with an inter-gate insulating filminterposed therebetween. The accumulation layer and control gate areformed of polycrystalline silicon layer. The gate insulating film isformed of a silicon oxide film. The inter-gate insulating film is formedof a silicon oxide film or an ON film, NO film or ONO film having alaminated structure of a silicon oxide film and silicon nitride film.The control gates of the memory cells MC which are arranged on the samerow are commonly connected to a corresponding one of word lines WL0 toWLm. Further, the drains of the memory cells MC which are arranged onthe same column are commonly connected to a corresponding one of bitlines BL0 to BLn. In addition, the sources of the memory cells MC arecommonly connected to the same source line SL. For convenience sake inthe following explanation, the word lines WL0 to WLm may be referred toas word lines WL and the bit lines BL0 to BLn may be referred to as bitlines BL in some cases.

The row decoder (not shown) selects any one of the word lines WL and thecolumn decoder selects any one of the bit lines BL.

Returning to FIG. 1, when data is read, the sense amplifier 7 reads datafrom the memory cell MC connected to the word line WL selected by therow decoder and the bit line BL selected by the column decoder andamplifies the data.

The verification circuit 8 writes write data given from the I/O buffer 4to the memory cell MC. The verification circuit 8 outputs data read bythe sense amplifier 7 to outside through the I/O buffer 4. Further, theverification circuit 8 executes a verification operation using data readby the sense amplifier 7 and write data. The verification operation isan operation for verifying whether or not data write or erase has beencarried out properly.

The analyzing circuit 9 analyzes a command given from the I/O buffer 4using an address given from the input buffer 3. A result of commandanalysis is output to the microcomputer 2 and the oscillation circuit10.

The oscillation circuit 10 generates a clock based on the result ofcommand analysis and supplies the clock to the microcomputer 2. The CPU20 of the microcomputer 2 is operated synchronously with the clock.

The power source circuit 11 is provided with a charge pump circuit forraising a voltage given from outside. A voltage necessary for write,read and erase of the data in the memory cell is generated under thecontrol of the microcomputer 2 and the control circuit 12.

The holding circuit 13 holds protect information. The protectinformation is the following information. The memory cell array includesa memory cell MC whose data is prohibited to be updated or erased. Theinformation indicating which memory cell MC data is prohibited to beupdated or erased is the protect information for protecting these memorycell MCs. By referring to the protect information, the microcomputer 2can determine whether or not data should be updated or erased in thememory cell MC instructed to be accessed.

The control circuit 12 directly controls the operations of the powersource circuit 11 and the sense amplifier 6 following the control of themicrocomputer 2. FIG. 3 is a block diagram showing the configuration ofthe control circuit 12.

As shown in the Figure, the control circuit 12 includes a register 30and a control decoder 31. The register 30 holds data (instruction) givenfrom the microcomputer 2. An automatic operation termination signal isgiven to the register 30 as a reset signal. The automatic operationtermination signal is a signal given from the microcomputer 2 and “0”when the aforementioned automatic operation mode is selected and “1”when the non-automatic operation mode is selected. When the automaticoperation termination signal is “1”, the register 30 is reset. An updateenable signal is given to the register 30 from the microcomputer 2. Whenthe update enable signal is “1”, the register 30 can fetch data into theinside. The control decoder 31 decodes an instruction held by theregister 30. Then, the operations of the power source circuit 11 and thesense amplifier 7 are controlled based on data obtained by decoding.

The flash memory configured as described above has the following effect(1).

(1) Acceleration of Operating Speed of Semiconductor Memory Device (No.1).

The automatic operation of the flash memory is achieved by a methodusing a state machine circuit or a logic circuit or a method by controlby the microcomputer. Because the command can be given to plural circuitblocks at the same time when the logic circuit is used for control, theoperating speed of the flash memory can be improved; however, thequantity of wirings is large and the wiring system is complicated.

The control by the microcomputer can reduce the quantity of wiringslargely as compared to the control by the logic circuit. However, themicrocomputer cannot give any command to the plural circuit blocks atthe same time. Further, because the bit count which can be handled islimited, sometimes, plural instructions or data need to be given severaltimes in order to perform a single operation. Thus, the operating speedis slow as compared to the control by the logic circuit.

According to this embodiment, the circuit block which performs aspecified routine processing, such as a voltage generating operation andverification operation in the sense amplifier, is controlled usinghardware instead of the microcomputer. More specifically, the controlcircuit 12 is provided as well as the microcomputer 2. The controlcircuit 12 incorporates a decoder (logic circuit) configured to executethe voltage generating operation or the verification operation. Thedecoder receives and decodes a instruction with several bit (forexample, 8 bits) given from the microcomputer 2 to generate acomplicated control instruction of 8 bits or more. The decoder controlsthe power source circuit 11 and the sense amplifier 7 using generatedcontrol instruction. That is, the microcomputer 2 does not provide allthe signals necessary for generation of voltage and verificationoperation and the control circuit generates a detailed control signal.Thus, for the control of the power source circuit 11 and the senseamplifier 7, the processing by the microcomputer 2 can be minimized toimprove the operating speed of the flash memory.

Further, the microcomputer 2 does not output a number of signals, sothat spare time for processing increases as compared to a conventionalexample. Thus, another instruction can be executed in such created sparetime. As a result, the microcomputer 2 can execute a larger number ofinstructions as compared to the conventional example, thereby achievingacceleration of the flash memory.

Second Embodiment

Next, a semiconductor memory device of according to a second embodimentof the present invention will be described. This embodiment concerns amethod of controlling the power source circuit 11 when the flash memorymakes transition to the automatic operation mode from the non-automaticoperation mode in the first embodiment. FIG. 4 is a block diagramshowing the configuration of the NOR type flash memory of thisembodiment.

As shown in the Figure, the flash memory 1 of this embodiment includesthe configuration of FIG. 1 described as the first embodiment with aswitch circuit 14. The switch circuit 14 switches an instruction to beinput to the control circuit 12. The other configuration is the same asthat in the first embodiment and description thereof is omitted.

The switch circuit 14 will be described with reference to FIG. 5. FIG. 5is a block diagram showing the configuration of the control circuit 12and the switch circuit 14.

As shown in FIG. 5, the switch circuit 14 includes a selection circuit40, an updating circuit 41, and a register value decoder 42. Theselection circuit 40 selects any one of data (instruction) from themicrocomputer 2 and startup decode value based on an output signal ofthe register value decoder 42. Then, any one selected is given to theregister 30 of the control circuit 12. The data from the microcomputer 2is an operation instruction of the control circuit 12 by themicrocomputer 2. The startup decode value is an instruction for starting(or booting) a charge pump circuit in the power source circuit 11.Therefore, when the startup decode value is given, the control circuit12 instructs the power source circuit 11 to start the charge pumpcircuit. The startup decode value may be a signal always given to theselection circuit 40 by a memory device such as a register, or may be asignal given together with the automatic operation command from outside.That is, a command factor signal input from outside may be decoded bythe analyzing circuit 9 to generate the startup decode value and thestartup decode value may be given to the switch circuit 14.

The register value decoder 42 decodes an output signal (that is, aninstruction held in the register 30) of the register 30 in the controlcircuit 12. If the register 30 is in reset state as a result of decode,decoder 42 outputs “1” and otherwise, outputs “0”. If the output of theregister value decoder 42 is “1”, the selection circuit 40 selects thestartup decode value and if it is “0”, data from the microcomputer 2 isselected.

The updating circuit 41 includes an OR gate 43 and an AND gate 44. TheOR gate 43 executes OR operation between an output signal of theregister value decoder 42 and an update enable signal given from themicrocomputer 2. The update enable signal is a signal which is “1” whenthe microcomputer 2 instructs the register 30 to fetch data. The ANDgate 44 executes AND operation between the output signal of the OR gate43 and a clock given from the oscillation circuit 10. Then, the outputsignal of the AND gate 44 is given as the update instruction to theregister 30 in the control circuit 12. That is, if the output of the ANDgate 33 is “1”, the register 30 fetches an instruction selected by theselection circuit 40. Consequently, the control decoder 31 controls thepower source circuit 11 based on an instruction fetched into theregister 30.

Next, the operation of the flash memory 2 having the above-describedconfiguration will be described with reference to FIGS. 4 to 7particularly by paying attention to a transition from the non-automaticoperation mode (second operation mode) to the automatic operation mode(first operation mode). FIG. 6 is a flow chart showing an operation ofthe flash memory and FIG. 7 is a timing chart showing statuses ofvarious signals and the register 30.

First, it is assumed that the flash memory 1 is in the non-automaticoperation mode (in step S10 and before time t1 in FIG. 7). Under thenon-automatic operation mode, the automatic operation command isspecified as “0”. The automatic operation command is an instructiongiven from outside and an instruction for operating the flash memory 2on the automatic operation mode. When the automatic operation command isspecified as “0”, the analyzing circuit 9 recognizes that it shouldoperate under the non-automatic operation mode and notifies theoscillation circuit 10 and the microcomputer 2 thereof. Consequently,the oscillation circuit 10 stops generation of clock. The microcomputer2 specifies the automatic operation termination signal as “1”. When theautomatic operation termination signal is specified as “1”, the register30 of the control circuit 12 is reset. Further, because the register 30is reset, the output of the register value decoder 42 is “1”. Therefore,the selection circuit 40 selects a startup decode value and gives it tothe register 30. However, because the output of the AND gate 44 is “0”at this time, the register 30 does not fetch the startup decode valuegiven from the selection circuit 40. As a result, the microcomputer 2 isin the non-operating state, so that the flash memory 2 is operated onthe non-automatic operation mode.

Next, it is assumed that “1” is input as the automatic operation commandat time t1 for transition from the non-automatic operation mode to theautomatic operation mode (step S11). Then, the analyzing circuit 9recognizes that it should be operated on the automatic operation modeand notifies the oscillation circuit 10 and the microcomputer 2 thereof.Consequently, the oscillation circuit 10 generates a clock (step S12).The microcomputer 2 specifies the automatic operation termination signalas “0” (step S13). When the automatic operation termination signal is“0”, the register 30 in the control circuit 12 is released from thereset state (step S14). FIG. 7 describes a timing in which the automaticoperation command signal is changed from “0” to “1” and a timing inwhich the automatic operation termination signal is changed from “1” to“0”. However, usually, the change timing of the automatic operationtermination signal is delayed because a specified time is needed for themicrocomputer 2 to be started.

Consequently, the output of the AND gate 44 is “1”. That is, because theoutput of the register value decoder 42 is “1”, the output of the ORgate 43 is “1”. Because a clock is generated in that condition, theoutput of the AND gate 44 is “1”. As a result, the register 30 fetchesthe startup decode value given from the selection circuit 40 (step S15,time t2).

When the register 30 fetches the startup decode value, the controldecoder 31 decodes the startup decode value and instructs the powersource circuit 11 to start the charge pump circuit. At the same time,the register 30 is released from the reset state and thus the output ofthe register value decoder 42 turns to “0” (step S16, time t3).

When the output of the register value decoder 42 is changed to “0”, theselection circuit 40 comes to fetch data from the microcomputer (stepS17, time t4). Because the output of the register value decoder 42 is“0” at this time, the output of the OR gate 43 is “0” and the register30 does not fetch data of the microcomputer. As a result, preparationfor the power source circuit 11 to operate under the automatic operationmode is completed.

At a timing when the update enable signal given from the microcomputer 2turns to “1”, the register 30 fetches data from the microcomputer 2(step S18, time t5, t6). Consequently, the flash memory is operated onthe automatic operation mode (step S19). After that, when the register30 fetches data from the microcomputer 2 at a timing of the updateenable signal, the operation of the control circuit 12 is controlled bythe microcomputer 2.

The transition from the automatic operation mode to the non-automaticoperation mode is carried out as follows. First, the automatic operationcommand is specified as “0”. As a result, the oscillation circuit stopsthe generation of the clock. Further, the automatic operationtermination signal is specified as “1” and the update enable signal isfixed to “0”. As a result, the register 30 is in the reset state, sothat the output of the register value decoder 42 turns to “1”, therebyprohibiting updating of the register 30. Then, the startup decode valueof the selection circuit 40 is selected. As a result, the controlcircuit 12 is operated without any control by the microcomputer 2.

As described above, the semiconductor memory device according to thesecond embodiment of the invention obtains the following effect (2) aswell as the effect (1) described in the first embodiment.

(2) Improvement of Operating Speed of Semiconductor Memory Device (No.2).

One of demerits (overhead) that the processing of the automaticoperation of the flash memory as compared to the control by the logiccircuit is delay of startup of the charge pump circuit.

In the flash memory, usually, the charge pump circuit is in thenon-operating condition except when the automatic operation mode isselected. This aims at preventing reduction of power consumption andgeneration of noise source. Therefore, when the automatic operationcommand is input to the flash memory, first, the charge pump circuitneeds to be started. It takes a relatively long time when the start ofthe charge pump circuit is carried out by the microcomputer for thefollowing reasons. That is, the microcomputer 2 is not operated untiljust before the non-automatic operation mode is changed to the automaticoperation mode. Therefore, the start of the charge pump circuit iscarried out by:

(a) analyzing automatic operation command input from outside with theanalyzing circuit 9;

(b) as a result of analysis, microcomputer 2's starting its operation;and

(c) microcomputer 2's reading a charge pump circuit startup instructionafter its operation is started.

That is, even if the automatic operation command is input, it isdifficult to dispatch the startup instruction immediately and usually,it takes several hundreds ns since the automatic operation command isinput.

The charge pump circuit cannot be started immediately just after a startinstruction is given and it needs some time for the charge pump circuitto be started. Thus, under the control by the microcomputer 2, timeuntil the charge pump circuit is enabled to be operated since theautomatic operation command is input, that is, time until the flashmemory is enabled to perform automatic operation is increased.

According to the configuration of this embodiment, the startup decodevalue which is an instruction for starting the charge pump circuit isgiven to the control circuit 12 independently of the control of themicrocomputer 2. Then, a signal which serves as trigger for fetching thestartup decode value is given by the register value decoder 42 and theupdating circuit 41 of the switch circuit 14. That is, if the timing forfetching an instruction of the register 30 relies upon an update enablesignal which is given from the microcomputer 2, the start of the chargepump circuit is delayed even if the startup decode value is given fromother than the microcomputer 2. Thus, according to this embodiment, asthe timing for fetching an instruction of the register 30, the output ofthe register value decoder 42 is used by using a fact that the register30 is in the reset state under the non-automatic operation mode.Consequently, it becomes possible to input the startup decode value tothe register 30 earlier than the microcomputer 2 becomes enabled to beoperated, and as a result, the charge pump circuit can be started upquickly. Consequently, the high speed operation of the flash memory isenabled.

Third Embodiment

Next, a semiconductor memory device according to a third embodiment ofthe present invention will be described. This embodiment concernsvoltage updating timing in the power source circuit 11 of the secondembodiment. Description of the flash memory 2 is omitted because theentire configuration thereof is the same as shown in FIG. 4 of thesecond embodiment and then, only different points from the first andsecond embodiments will be described. FIG. 8 is a block diagram showingthe configuration of the control circuit 12, the switch circuit 14 andthe power source circuit 11 included in the flash memory 1.

Data given to the switch circuit 14 from the microcomputer 2 is (M+N),which is 8 bits, where for example, M=1 bit and N=7 bits. For example, Mbit is 1 bit which is the highest bit of the 8 bits and N bit is lower 7bits of the 8 bits. Of these (M+N) bits, N bit data is controlinformation of the power source circuit 11 and used in the controlcircuit 12. On the other hand, data of the M bit is used as informationof the update timing of the output voltage in the power source circuit11. Of course, the bit count is not limited to the aforementioned one.

As shown in the figure, the power source circuit 11 includes a register50, flip-flop 51, digital-to-analog converter, regulator 53 and ANDgates 54, 55. The register 50 holds a set value given from themicrocomputer 2. The set value is data corresponding to the value of avoltage to be generated by the power source circuit 11. The flip-flop 51holds a set value, which is transferred from the register 50. Thedigital-to-analog converter 52 is supplied with reference power in orderto convert the set value held by the flip-flop 51 from digital value toanalog value. The regulator 53 generates a voltage corresponding to theset value and outputs the voltage, according to the value obtained bythe digital-to-analog converter 52. The AND gate 54 executes ANDoperation between the clock and the update enable signal. The register50 fetches the set value at a timing when the result of arithmeticoperation of the AND gate 54 is “1”. The AND gate 55 executes ANDoperation between the clock and the M bit of data held by the register30 of the control circuit 12. Then, the flip-flop 51 fetches the setvalue at a timing when the result of arithmetic operation of the ANDgate 55 is “1”.

Next, the operation of the power source circuit 11 having theabove-described configuration will be described with reference to FIG.9. FIG. 9 is a flow chart showing the operation of the power sourcecircuit.

As shown in FIG. 9, under the automatic operation mode (step S20), theset value is given to the register 50 from the microcomputer 2 (stepS21). If the update enable signal is “1” (step S22: YES), the output ofthe AND gate 54 is “1” and thus the set value is fetched into theregister 50 (step S23). In the case of the update timing, that is, ifthe M bit of an instruction held by the register 30 is “1” (step S24:YES), the output of the AND gate 55 is “1” and thus the set value isfetched into the flip-flop 51 (step S25). A voltage is generated by thedigital-to-analog converter 52 and the regulator 53 according to the setvalue held by the flip-flop 51 (step S26). Further, if there is a nextset value (step S27: YES), the next set value is given to the register50 by the microcomputer 2 within the spare time for voltage control(step S28) and operation subsequent to step S22 is repeated.

A specific example of the above-described operation will be describedwith reference to FIG. 10. FIG. 10 is a timing chart showing transitionof an instruction in the register 30, the set value in the register 50and the flip-flop 51 of the power source circuit 11 and the outputvoltage of the regulator 53.

As shown in FIG. 10, assume that an instruction of voltage control 1using voltage V2 is given to the register 30 at time t10, a set value V2is given to the register 50 and M bit of the instruction of the voltagecontrol 1 is “1” (update timing). Then, the set value V2 in the register50 is given to the flip-flop 51 and the voltage V2 is output by theregulator 53.

Next, assume that the microcomputer 2 inputs a next set value V3 to theregister 50 at time t11 within the spare time for control. Then,although the set value V3 is fetched into the register 50, it is notfetched into the flip-flop 51 because it is not update timing.

Next, an instruction of voltage control 2 using the voltage V2 is givento the register 30 at time t12. Because this instruction does not changethe voltage, the M bit of the instruction of the voltage control 2 is“0”. Therefore, the set value V3 in the register 50 is not fetched intothe flip-flop 51 and the regulator 53 continues to output the voltageV2.

Next, an instruction of voltage control V3 using the voltage V3 is givento the register at time t13. Because this instruction accompanies changeof the voltage, the M bit of the instruction of the voltage control 3 is“1”. That is, the set value V3 in the register 50 is fetched into theflip-flop 51 because it is the update timing. Consequently, theregulator 53 changes the output voltage from V2 to V3 and outputs it.

As described above, the semiconductor memory device according to thethird embodiment of the invention can obtain the following effect (3) aswell as the effects (1), (2) described in the first and secondembodiments.

(3) Improvement of Operating Speed of Semiconductor Memory Device (No.3).

Various values of the voltages are needed for write, erase or readduring the automatic operation of the flash memory. The change of thevoltage is often carried out at a timing of updating the register 30 inthe control circuit 12.

In the configuration of this embodiment, the register 50 and theflip-flop 51 capable of holding the set values are provided in series inthe power source circuit 11. The respective set value fetch timings aredifferentiated. More specifically, the set value is fetched in at atiming of the update enable signal in the register 50 on a pre-stage.Further, the set value is fetched based on part of bits in aninstruction held by the register 30 in the flip-flop 51 on a post stage.For this purpose, part of the bits of an instruction held by theregister 30 is supplied with not the content of control of the powersource circuit 11 by the control circuit 12 but a meaning which servesas trigger for updating of the voltage of the voltage circuit 11.Additionally, the microcomputer 2 inputs a next set value to theregister 50 in a period having a small amount of processing. Even if anew set value is input to the register 50, the output voltage of thepower source circuit 11 is never changed until the aforementionedtrigger in an instruction of the register 30 is established.

As described above, the microcomputer 2 can input the set value into thepower source circuit 11 in the spare time and prepare the set value inthe power source circuit 11. As a result, load on the microcomputer 2 isreduced and the processing efficiency of the microcomputer 2 isimproved, so that the power source circuit 11 can change the voltagerapidly. Consequently, the operating speed of the flash memory can beimproved.

Fourth Embodiment

Next, a semiconductor memory device according to a fourth embodiment ofthe present invention will be described. This embodiment concerns theconfiguration and operation of the verification circuit 8 in any of thefirst to third embodiments. Hereinafter, only different points from thefirst to third embodiments will be described. FIG. 11 is a block diagramof a memory cell array included in the memory cell portion 6 of theflash memory 1 of this embodiment.

As shown in FIG. 11, the memory cell array has three regular blocksRBLK0 to RBLK2 and four boot blocks BBLK0 to BBLK3. Hereinafter if theregular blocks RBLK0 to RBLK2 are not differentiated, the regular blockswill be called just regular block RBLK and if the boot blocks BBLK0 toBBLK3 are not differentiated, the boot blocks will be called just bootblock BBLK. If the regular block RBLK and the boot block BBLK are notdistinguished, they will be called just block.

The regular block RBLK and the boot block BBLK are a group of the memorycell MCs. The data held in the memory cell MCs in each block are erasedat a time. That is, the block size is equal to erase unit. A differencebetween the regular block RBLK and the boot block BBLK is memory sizeand application field. As for the memory size, the regular block RBLKhas a larger size than the boot block BBLK and the memory size of theregular block RBLK is equal to the memory size of four boot blocks BBLK.Next, as for the application field, the regular block RBLK is used as astorage for data which is rewritten frequently by a user, such as imagesand sound. On the other hand, although the boot block BBLK is used as astorage for start program of the circuit block or the like which hassmall data size and is important data for the system.

Next, the verification operation of the regular block RBLK and the bootblock BBLK by the verification circuit 8 will be described simply withreference to FIG. 12. FIG. 12 is a conceptual diagram showing theregular block RBLK and the boot block BBLK, indicating an access statusat the time of a verification operation.

As shown in FIG. 12, the verification operation is carried out in thesize of the regular block RBLK regardless of the regular block RBLK andboot block BBLK. In this example of the embodiment, the memory size ofone regular block RBLK is equal to the memory size of four boot blocksBBLK. Thus, if erase of the boot block BBLK2 and verification of theerase thereof are carried out, verification of erase of all four bootblocks BBLK0 to BBLK3 is carried out.

Next, the configuration of the verification circuit 8 included in theflash memory 1 of this embodiment will be described with reference toFIG. 13. FIG. 13 is a circuit diagram of the verification circuit 8.

As shown in FIG. 13, the verification circuit 8 includes registers 60-0to 60-3, 65, determination circuit 62, output circuit 63 and comparisoncircuit 64.

The registers 60-0 to 60-3 set a flag indicating selection/non-selectionof the boot block BBLK based on a boot block selection signal given fromthe microcomputer 2. The registers 60-0 to 60-3 correspond to therespective boot blocks BBLK0 to BBLK3. when the data is updated (writeor erase) in any one of the boot blocks BBLK0 to BBLK3 and verificationis needed, “1” is held in any one of the corresponding registers 60-0 to60-3 and “0” is held in the others. The boot block BBLK in which data isupdated actually is called selected boot block BBLK depending on a casebelow.

For example, assume that data in the boot block BBLK2 is updated. Inthis case, the selected boot block is the boot block BBLK2. Thus, asdescribed in FIG. 12, the verification is executed for all the four bootblocks BBLK0 to BBLK3 and only the register 60-2, which corresponds toBBLK2, sets the flag. Therefore, only the register 60-2 holds “1” andthe other registers 60-0, 60-1 and 60-3 hold “0”.

The determination circuit 62 determines whether or not the memory cellMC in which verification is executed is contained in the selected bootblock BBLK. The determination circuit 62 includes AND gates 70-0 to 70-3and a NOR gate 71. The AND gates 70-0 to 70-3 execute AND operationbetween an address signal indicating the boot blocks BBLK0 to BBLK3 anda flag held by the registers 60-0 to 60-3. An address signal indicatingthe boot blocks BBLK0 to BBLK3 is a signal which is given from themicrocomputer 2 and indicates a block address of the memory cell MCholding read data in which verification is executed. That is, if thememory cell MC is contained in the boot block BBLK0, an address signalindicating the boot block BBLK0 is “1” and if it is contained in theboot block BBLK1, an address signal indicating the boot block BBLK1 is“1”. The NOR gate 71 executes NOR operation between the output of theAND gates 70-0 to 70-3 and a regular block selection signal. The regularblock selection signal is given from the microcomputer 2 and set to “1”if data of the regular block RBLK is updated and “0” in other cases.

Assume that as described above, the data in the boot block BBLK2 isupdated. Then, when the memory cell MC contained in the boot block BBLK2is verified, the address signal indicating the boot block BBLK2 is “1”and the output of the AND gate 70-2 is “1”. The outputs of the other ANDgates 70-0, 70-1, 70-3 are “0” and the output of the NOR gate 71 is “0”.

If data in the regular block RBLK is updated, the output of the NOR gate71 is “0”.

On the other hand, if the memory cell MCs contained in the boot blocksBBLK0, BBLK1 and BBLK3 are verified, the address signal indicating theboot blocks BBLK0, BBLK1 and BBLK3 is “1”. However, because theregisters 60-0, 60-1 and 60-3 hold “0”, the outputs of all the AND gates70-0 to 70-3 are “0” and the output of the NOR gate 71 is “1”.

The comparison circuit 64 compares data read by the sense amplifier 6with write original data (“1” in case of erase) so as to determinewhether or not accurate data is held in the memory cell MC. If both ofthem coincide as a result of the comparison, “1” is output andotherwise, “0” is output.

The register 65 holds the comparison result of the comparison circuit64. The register 65 fetches the comparison result according to averification result update signal given from the microcomputer 2 and isreset by a verification result reset signal.

The output circuit 63 outputs a verification result and write data basedon the output of the determination circuit 62 and a comparison resultheld in the register 65. The output circuit 63 includes AND gates 80, 81and OR gate 82. The AND gate 80 executes AND operation between thecomparison result held by the register and an inversion signal of theoutput of the NOR gate 71. The OR gate 82 executes OR operation betweenthe output of the AND gate 80 and the output of the NOR gate 71. Then,an operation result of the OR gate 82 is output as a final verificationresult. The AND gate 81 executes OR operation between the write originaldata and the inversion signal of the output of the NOR gate 71.

Therefore, if all the outputs of the AND gates 70-0 to 70-3 are “0” andthe output of the NOR gate 71 is “1”, the output (verification result)of the NOR gate 82 is forced to be “1”, that is, verification OK.Further, the output (write data) of the AND gate 81 is fixed to “0”forcibly. On the other hand, if the output of the NOR gate 71 is “0”,the outputs of the NOR gate 82 and AND gate 81 depend on the comparisonresult and write original data held in the register 65.

The operation of the verification circuit 8 having the above-describedconfiguration when data of the memory cell MC is updated will bedescribed with reference to FIG. 14. FIG. 14 is a flow chart of theoperation of the verification circuit 8. The boot block BBLK and regularblock RBLK including a memory cell MC whose data is updated are calledselected block depending on a case if they are not distinguished fromeach other.

If a block (selected block) whose data is to be updated is boot blockBBLK (step S30: YES), the microcomputer 2 starts setting of theregisters 60-0 to 60-3 (step S31). The microcomputer 2 sets a boot blocknumber i to “0” (step S32) and determines whether or not the boot blockBBLKi is a selected block and unprotected (step S33). Whether or not itis a selected block can be grasped by referring to an address signal andwhether or not it is protected can be grasped by referring to protectinformation in the holding circuit 13.

Because data of a given block is updated if it is a selected block andnot protected (step S33: YES), the microcomputer 2 set a flag on theregisters 60-0 to 60-3 corresponding to that block (step S34). If datawrite or erase is carried out in the boot block BBLK2 as describedabove, the register 60-2 holds “1”. Then, processing of steps S33 to S34is repeated until i becomes a maximum value (because this embodiment hasfour boot blocks BBLK, i=4−1=3, step S35) (step S36).

The setting of the registers 60-0 to 60-3 is thus finished. If data isupdated in any of the boot blocks BBLK, “1” is held in the correspondingregisters 60-0 to 60-3. Of course, the number of the boot blocks BBLKwhich are to be updated is not restricted to 1 but may be plural.Further, even if one of the boot blocks BBLK is a selected block, if theboot block BBLK is protected, no data is updated and thus, the registers60-0 to 60-3 corresponding to the given boot block BBLK continue to hold“0”.

When a block whose data should be updated exists as a result oftermination of step S35 (step S35: YES), or when the selected block isthe regular block RBLK (step S30: NO) while the selected block is notprotected (step S38: YES), data in the selected block is updated (stepS39). That is, data write or erase is carried out in the selected block.If NO in steps S37, S38, the processing is terminated.

When the data update of step S39 is terminated, the verificationoperation is executed next (step S40). First, the microcomputer 2 setsthe row address and column address at a head address (step S41).

For example, if the regular block RBLK0 is a selected block, the headaddress is an address corresponding to the head memory cell MC of theregular block RBLK0. The final address is an address corresponding to afinal memory cell MC of the regular block RBLK0.

On the other hand, if one of the boot block BBLK is selected as shown inFIG. 12, the head address is an address corresponding to the head memorycell of the boot block BBLK0. The final address is an addresscorresponding to the final memory cell MC of the boot block BBLK3. Thisis because as described above, verification is executed about the fourboot blocks BBLK0 to BBLK3.

Then, data is read from a memory cell MC (called selected memory cell)corresponding to the aforementioned address and compared by thecomparison circuit 64. Consequently, whether or not data is updatedproperly in the selected memory cell is verified.

Further, whether or not a memory cell (selected memory cell) compared bythe comparison circuit is contained in the selected block is determined(step S42). In this determination, the microcomputer 2 needs noprocessing. This is because the processing of step S42 is carried out bythe determination circuit 62. If the output of the NOR gate 71 is “0”,the selected memory cell is contained in the selected block and if it is“1”, the selected memory cell is not contained in the selected block.

First, a case where the selected memory cell is not contained in theselected block (step S42: No) will be described with reference to FIG.15. FIG. 15 is a block diagram of the verification circuit 8, indicatinga case where the selected block is the boot block BBLK2 and the selectedmemory cell MC is contained in the unselected boot block BBLK0.

As shown in the FIG. 15, “1” is held in the register 60-2 and “0” isheld in the registers 60-0, 60-1 and 60-3. Naturally, the regular blockselection signal is “0”. Further, because the selected memory cell iscontained in the boot block BBLK0, an address signal indicating the bootblock BBLK0 is “1” and a signal indicating the boot blocks BBLK1 toBBLK3 is “0”.

Consequently, the outputs of all the AND gates 70-0 to 70-3 are “0” inthe determination circuit 62 and the output of the NOR gate 71 is “1”.As a result, the output of the NOR gate 82 is “1” in the output circuit63. That is, verification is OKed regardless of a comparison result heldby the register 65 (step S43). The output of the AND gate 81 is fixed toa predetermined value forcibly (step S44). Although under theconfiguration of FIG. 15, the output of the AND gate 81 is fixed to “0”,this value may be fixed to “1”.

Next, a case where the selection memory cell is contained in theselected block (step S42: YES) will be described with reference to FIG.16. FIG. 16 is a block diagram of the verification circuit 8, indicatinga case where the selected block is the boot block BBLK2 while theselected memory cell MC is contained in the selected boot block BBLK2.

As shown in FIG. 16, because the selected memory cell is contained inthe boot block BBLK2, the address signal indicating the boot block BBLK2is “1”. Therefore, the output of the AND gate 70-2 in the determinationcircuit 62 is “1” while the output of the NOR gate 71 is “0”.

Thus, the output of the OR gate 82 in the output circuit 63 isdetermined depending on the output of the AND gate 80, that is, acomparison result held by the register 65. That is, when the comparisoncircuit outputs “1”, verification is OKed and if it outputs “0”,verification is wrong (step S45). The output of the AND gate 81 isdetermined by the write original data. That is, if the write originaldata is “1”, the write data is “1” and if the write original data is“0”, the write data is “0” (step S46).

In the meantime, if the regular block RBLK is a selected block, all theselected memory cells are contained in the selected block. This isbecause the regular block RBLK is a unit which executes verification. Inthis case, microcomputer 2 reflects the data held in the register 65 andthe write original data to the output of the output circuit 63 bysetting the regular block selection signal to “1”.

After steps S44 and S46, if the row address and column address are notthe final address (steps 47: NO), the microcomputer 2 sets the rowaddress and column address to a next address (step S48) and theprocedure returns to step S42. If the row address and column addressreaches the final address (step S47: YES) and verification is executedin another block (step S48: YES), the procedure returns to step S30, inwhich the aforementioned processing is repeated. Unless the processingis executed (step S48: NO), the procedure is completed.

As described above, the semiconductor memory device according to thefourth embodiment of the invention can obtain the following effect (4)as well as the effects (1) to (3) described in the first to thirdembodiments.

(4) Improvement of Operating Speed of Semiconductor Memory Device (No.4).

The boot block BBLK is a segmentation area of ¼ block size with respectto the regular block RBLK according to this embodiment. Generally, ifverification is carried out in the boot block BBLK by the microcomputer2, verification is executed only in the selected boot block BBLK.

However, the range to be verified naturally differs between the bootblock BBLK and the regular block RBLK. Thus, according to theabove-mentioned method, the microcomputer 2 needs to determine whetheror not the given address exists within the selected boot block BBLK foreach address. Further, if data is updated about plural boot blocks BBLK,after whether or not verification is terminated on a single boot blockBBLK is determined, whether or not a next address exists in the bootblock BBLK needs to be determined for each address. This processing isalso needed when verification is carried out on the regular block RBLK.Usually, the determination processing by the microcomputer 2 includes atleast two instructions, namely, arithmetic operation instruction andbranch instruction. Therefore, in case of a 16-bit microcomputer 2,(determination processing twice)×two instructions=four instructionsneeds to be repeated 16,636 times. As a result, time of about 26 ms isneeded to determine whether or not the given address indicates the bootblock BBLK.

The configuration of this embodiment does not need the aforementionedfour instructions, thereby achieving high speed verification operation.According to this embodiment, the unit for verification is specified tothe regular block size as a common unit between the regular block RBLKand the boot block BBLK. If the selected block is the boot block BBLK, acomparison result in the comparison circuit 64 is reflected on averification result of the selected boot block BBLK. Then, theverification result of the unselected boot block BBLK is forced to beOKed by the output circuit 63. The microcomputer 2 does not determinewhether or not the selected memory cell is included in a selected bootblock BBLK and this determination is carried out by the determinationcircuit 62 provided on the verification circuit 8. Consequently, load onthe microcomputer 2 is reduced so as to improve the operating speed ofthe flash memory.

Although a case where the size of the boot block BBLK is ¼ the size ofthe regular block RBLK has been described in this embodiment, theembodiment is not restricted to this size. FIG. 17 is a block diagram ofthe regular block RBLK and the boot block BBLK. The boot block BBLK maybe obtained by dividing the regular block RBLK by (k+1) (k is a positiveinteger). FIG. 18 shows the configuration of the verification circuit 8in this case. As shown in FIG. 18, selection information of the bootblocks BBLK0 to BBLKk is stored in the registers 60-0 to 60-k. The ANDgates 70-0 to 70-k execute AND operation between a flag within theregisters 60-0 to 60-k and an address signal indicating the boot blocksBBLK0 to BBLKk, respectively.

According to the semiconductor memory devices of the first to fourthembodiments of the present invention, the operating speed can beimproved effectively by constructing part of the flash memory forcontrolling the microcomputer 2 into hardware. In the meantime, althoughthe above embodiments have been described about the NOR type flashmemory as an example, they can be applied to, for example, NAND typeflash memory. Although in the above embodiments, a case where the powersource circuit 11 and the sense amplifier 7 are controlled by thecontrol circuit 12 has been described, other circuit blocks may becontrolled by the control circuit 12. Its control content is not limitedto those described in the embodiments. Further, according to theembodiments, when the regular block is selected, the output of the NORgate 71 is set to “0” by a regular block selection signal. However, whenthe regular block is selected, all the registers 60-1 to 60-3 may beforced to be “1” while all signals indicating BBLK0 to BBLK3 may beforced to be set to “1” instead of using the regular block selectionsignal.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A memory system comprising: a microcomputer; a power source circuitincluding a first resister, an AND gate, and a flip-flop connected tothe first resister and the AND gate; a switch circuit; a control circuitincluding a second resistor, the second register being connected to theswitch circuit; wherein the microcomputer sends first data to the firstresister, and second data from the second resistor and a clock are inputto the AND gate.
 2. The memory system according to claim 1, wherein themicrocomputer sends third data to the switch circuit.
 3. The memorysystem according to claim 1, wherein the switch circuit includes aselection circuit to which a third data is input from the microcomputerand sending the third data to the second resistor.
 4. The memory systemaccording to claim 2, wherein a first signal is input to the firstresistor.
 5. The memory system according to claim 4, wherein the switchcircuit includes an OR gate to which the first signal is input andoutputting an operation result to the second resistor.
 6. The memorysystem according to claim 5, wherein the third data is (M+N) bits (M, Nare natural numbers) and the second data is M-bit of the third data. 7.The memory system according to claim 6, wherein the second resistorsends N-bit of the third data to a control decoder.
 8. The memory systemaccording to claim 6, wherein the N-bit of the third data is a controlsignal of the power source circuit, and the M-bit of the second data isupdate timing information of the power source circuit.
 9. The memorysystem according to claim 6, wherein the first data corresponds to a setvalue of a voltage to be generated by the power source circuit.
 10. Thememory system according to claim 4, wherein when the first signal is in“H” level, the first resister sends the first data to the flip-flop. 11.The memory system according to claim 10, wherein when the M-bit is in“H” level, the flip-flop sends the first data to the digital-analogconverter.
 12. The memory system according to claim 6, wherein when theM-bit is in “H” level, the power source circuit operates based on thefirst data.
 13. The memory system according to claim 12, wherein asecond signal is input to the second resistor.
 14. The memory systemaccording to claim 13, wherein when the second signal is in “H” level,the operation of the power source circuit based on the first dataterminates.